1. Field
One or more embodiments relate to quickly processing a program through adaptation to an architecture having two execution modes among various types of processors.
2. Description of the Related Art
Various types of processors have been developed.
Although a basic function referred to as execution of a program has been maintained as is, a method and architecture for executing the basic function have been continuously modified and enhanced.
A processor may have at least one execution mode. An example of a processor having two execution modes may be a reconfigurable processor that performs a very long instruction word (VLIW) mode and a coarse grained architecture (CGA) mode.
In the VLIW mode, program operation may be performed through predetermined pipeline processing by patching an instruction from an instruction cache, which is the same as a general processor. In the CGA mode, program operation may be performed by reading configuration information of a processor from storage referred to as a configuration memory.
Configuration information of a processor may include information associated with a functional unit (FU) to be selected from among a plurality of FUs simultaneously executable, an operation to be performed within each FU, and the like.
Such a processor may share a single register file.
Due to dependency that a result value of VLIW may be used as an input of CGA, or a result value of CGA may be used as an input of VLIW, a single register file is used. Thus, it may not be possible to perform parallel processing with respect to two executions modes, which may result in consuming a large amount of resources.
A processor having two execution modes may process a program that has a different characteristic within a single program through different modes. For example, among processors, there is a processor that may execute two modes, for example, a VLIW mode and a CGA mode.
In the case of processing a general instruction, the processor may be operated in the VLIW mode. In the case of processing a loop, the processor may be operated in the CGA mode. This is to enhance the overall execution rate by accelerating a loop portion.
Two modes may be sequentially executed since dependency is present between the two modes although the processor operates in the different modes. For example, a result value of VLIW may be used as an input of CGA and thus, two modes need to be sequentially executed.
However, the above sequential execution may use a relatively large amount of resources in many operators. When an operation is performed in a single mode, nothing may occur in the other mode. Accordingly, performance for resources may be degraded.
In general, the result of VLIW may affect CGA. However, in the CGA mode, an operation may be generally performed on a large amount of data. Therefore, in many cases, a result value may be stored in a memory instead of being stored in a register file.
Although not always, it is possible to remove the dependency by the register file since a result value may be input in a memory area in the case of generating a program.
Further, although a memory storing a result value of CGA may be used for subsequent VLIW, it may also be adjusted in the case of generating a program. In general, the VLIW may be used to control a program or to process a small amount of operations and the CGA may be used to process a large amount of data operations at a time. Accordingly, dependency on a memory may be relatively small between the VLIW and the CGA. A relatively large amount of data migration may occur between CGA and subsequent CGA.